/*! \file bcm56960_a0_bcmtm_sid_alias.h
 *
 * File containing glue functions for Flexport and TDM library.
 */
/*
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#ifndef BCM56960_A0_BCMTM_SID_ALIAS_H
#define BCM56960_A0_BCMTM_SID_ALIAS_H



#include <bcmdrd/chip/bcm56960_a0_enum.h>

#define BCM56960_A0_IP_EXTRA_MEM_BASE          (BCM56960_A0_ENUM_COUNT + 1001)
#define BCM56960_A0_EP_EXTRA_MEM_BASE          (BCM56960_A0_ENUM_COUNT + 2001)
#define BCM56960_A0_IP_EXTRA_REG_BASE          (BCM56960_A0_ENUM_COUNT + 3001)
#define BCM56960_A0_EP_EXTRA_REG_BASE          (BCM56960_A0_ENUM_COUNT + 4001)
#define BCM56960_A0_MMU_EXTRA_REG_BASE         (BCM56960_A0_ENUM_COUNT + 5001)
#define BCM56960_A0_MMU_EXTRA_MEM_BASE         (BCM56960_A0_ENUM_COUNT + 6001)




/* IP Memories */
#define IDB_OBM0_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 1  )
#define IDB_OBM0_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 2  )
#define IDB_OBM0_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 3  )
#define IDB_OBM0_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 4  )
#define IDB_OBM0_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 5  )
#define IDB_OBM0_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 6  )
#define IDB_OBM0_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 7  )
#define IDB_OBM0_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 8  )
#define IDB_OBM0_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 9  )
#define IDB_OBM0_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 10 )
#define IDB_OBM0_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 11 )
#define IDB_OBM0_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 12 )
#define IDB_OBM0_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 13 )
#define IDB_OBM0_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 14 )
#define IDB_OBM0_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 15 )
#define IDB_OBM0_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 16 )
#define IDB_OBM1_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 17 )
#define IDB_OBM1_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 18 )
#define IDB_OBM1_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 19 )
#define IDB_OBM1_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 20 )
#define IDB_OBM1_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 21 )
#define IDB_OBM1_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 22 )
#define IDB_OBM1_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 23 )
#define IDB_OBM1_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 24 )
#define IDB_OBM1_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 25 )
#define IDB_OBM1_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 26 )
#define IDB_OBM1_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 27 )
#define IDB_OBM1_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 28 )
#define IDB_OBM1_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 29 )
#define IDB_OBM1_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 30 )
#define IDB_OBM1_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 31 )
#define IDB_OBM1_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 32 )
#define IDB_OBM2_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 33 )
#define IDB_OBM2_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 34 )
#define IDB_OBM2_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 35 )
#define IDB_OBM2_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 36 )
#define IDB_OBM2_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 37 )
#define IDB_OBM2_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 38 )
#define IDB_OBM2_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 39 )
#define IDB_OBM2_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 40 )
#define IDB_OBM2_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 41 )
#define IDB_OBM2_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 42 )
#define IDB_OBM2_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 43 )
#define IDB_OBM2_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 44 )
#define IDB_OBM2_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 45 )
#define IDB_OBM2_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 46 )
#define IDB_OBM2_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 47 )
#define IDB_OBM2_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 48 )
#define IDB_OBM3_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 49 )
#define IDB_OBM3_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 50 )
#define IDB_OBM3_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 51 )
#define IDB_OBM3_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 52 )
#define IDB_OBM3_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 53 )
#define IDB_OBM3_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 54 )
#define IDB_OBM3_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 55 )
#define IDB_OBM3_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 56 )
#define IDB_OBM3_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 57 )
#define IDB_OBM3_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 58 )
#define IDB_OBM3_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 59 )
#define IDB_OBM3_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 60 )
#define IDB_OBM3_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 61 )
#define IDB_OBM3_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 62 )
#define IDB_OBM3_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 63 )
#define IDB_OBM3_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 64 )
#define IDB_OBM4_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 65 )
#define IDB_OBM4_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 66 )
#define IDB_OBM4_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 67 )
#define IDB_OBM4_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 68 )
#define IDB_OBM4_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 69 )
#define IDB_OBM4_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 70 )
#define IDB_OBM4_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 71 )
#define IDB_OBM4_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 72 )
#define IDB_OBM4_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 73 )
#define IDB_OBM4_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 74 )
#define IDB_OBM4_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 75 )
#define IDB_OBM4_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 76 )
#define IDB_OBM4_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 77 )
#define IDB_OBM4_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 78 )
#define IDB_OBM4_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 79 )
#define IDB_OBM4_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 80 )
#define IDB_OBM5_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 81 )
#define IDB_OBM5_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 82 )
#define IDB_OBM5_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 83 )
#define IDB_OBM5_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 84 )
#define IDB_OBM5_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 85 )
#define IDB_OBM5_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 86 )
#define IDB_OBM5_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 87 )
#define IDB_OBM5_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 88 )
#define IDB_OBM5_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 89 )
#define IDB_OBM5_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 90 )
#define IDB_OBM5_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 91 )
#define IDB_OBM5_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 92 )
#define IDB_OBM5_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 93 )
#define IDB_OBM5_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 94 )
#define IDB_OBM5_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 95 )
#define IDB_OBM5_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 96 )
#define IDB_OBM6_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 97 )
#define IDB_OBM6_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 98 )
#define IDB_OBM6_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 99 )
#define IDB_OBM6_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 100)
#define IDB_OBM6_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 101)
#define IDB_OBM6_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 102)
#define IDB_OBM6_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 103)
#define IDB_OBM6_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 104)
#define IDB_OBM6_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 105)
#define IDB_OBM6_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 106)
#define IDB_OBM6_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 107)
#define IDB_OBM6_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 108)
#define IDB_OBM6_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 109)
#define IDB_OBM6_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 110)
#define IDB_OBM6_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 111)
#define IDB_OBM6_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 112)
#define IDB_OBM7_PRI_MAP_PORT0_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 113)
#define IDB_OBM7_PRI_MAP_PORT1_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 114)
#define IDB_OBM7_PRI_MAP_PORT2_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 115)
#define IDB_OBM7_PRI_MAP_PORT3_PIPE0m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 116)
#define IDB_OBM7_PRI_MAP_PORT0_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 117)
#define IDB_OBM7_PRI_MAP_PORT1_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 118)
#define IDB_OBM7_PRI_MAP_PORT2_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 119)
#define IDB_OBM7_PRI_MAP_PORT3_PIPE1m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 120)
#define IDB_OBM7_PRI_MAP_PORT0_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 121)
#define IDB_OBM7_PRI_MAP_PORT1_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 122)
#define IDB_OBM7_PRI_MAP_PORT2_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 123)
#define IDB_OBM7_PRI_MAP_PORT3_PIPE2m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 124)
#define IDB_OBM7_PRI_MAP_PORT0_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 125)
#define IDB_OBM7_PRI_MAP_PORT1_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 126)
#define IDB_OBM7_PRI_MAP_PORT2_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 127)
#define IDB_OBM7_PRI_MAP_PORT3_PIPE3m          (BCM56960_A0_IP_EXTRA_MEM_BASE + 128)

#define IS_TDM_CALENDAR0_PIPE0m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 129)
#define IS_TDM_CALENDAR0_PIPE1m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 130)
#define IS_TDM_CALENDAR0_PIPE2m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 131)
#define IS_TDM_CALENDAR0_PIPE3m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 132)

#define IS_TDM_CALENDAR1_PIPE0m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 133)
#define IS_TDM_CALENDAR1_PIPE1m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 134)
#define IS_TDM_CALENDAR1_PIPE2m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 135)
#define IS_TDM_CALENDAR1_PIPE3m                (BCM56960_A0_IP_EXTRA_MEM_BASE + 136)

#define TDM_CALENDAR0_PIPE0m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 137)
#define TDM_CALENDAR0_PIPE1m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 138)
#define TDM_CALENDAR0_PIPE2m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 139)
#define TDM_CALENDAR0_PIPE3m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 140)

#define TDM_CALENDAR1_PIPE0m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 141)
#define TDM_CALENDAR1_PIPE1m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 142)
#define TDM_CALENDAR1_PIPE2m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 143)
#define TDM_CALENDAR1_PIPE3m                   (BCM56960_A0_IP_EXTRA_MEM_BASE + 144)

/* EP memories  */
#define EGR_XMIT_START_COUNT_PIPE0m            (BCM56960_A0_EP_EXTRA_MEM_BASE + 1)
#define EGR_XMIT_START_COUNT_PIPE1m            (BCM56960_A0_EP_EXTRA_MEM_BASE + 2)
#define EGR_XMIT_START_COUNT_PIPE2m            (BCM56960_A0_EP_EXTRA_MEM_BASE + 3)
#define EGR_XMIT_START_COUNT_PIPE3m            (BCM56960_A0_EP_EXTRA_MEM_BASE + 4)



/* IPIPE Registers */
#define IDB_OBM0_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 1  )
#define IDB_OBM1_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 2  )
#define IDB_OBM2_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 3  )
#define IDB_OBM3_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 4  )
#define IDB_OBM4_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 5  )
#define IDB_OBM5_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 6  )
#define IDB_OBM6_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 7  )
#define IDB_OBM7_CONTROL_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 8  )
#define IDB_OBM0_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 9  )
#define IDB_OBM1_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 10 )
#define IDB_OBM2_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 11 )
#define IDB_OBM3_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 12 )
#define IDB_OBM4_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 13 )
#define IDB_OBM5_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 14 )
#define IDB_OBM6_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 15 )
#define IDB_OBM7_CONTROL_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 16 )
#define IDB_OBM0_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 17 )
#define IDB_OBM1_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 18 )
#define IDB_OBM2_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 19 )
#define IDB_OBM3_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 20 )
#define IDB_OBM4_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 21 )
#define IDB_OBM5_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 22 )
#define IDB_OBM6_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 23 )
#define IDB_OBM7_CONTROL_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 24 )
#define IDB_OBM0_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 25 )
#define IDB_OBM1_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 26 )
#define IDB_OBM2_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 27 )
#define IDB_OBM3_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 28 )
#define IDB_OBM4_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 29 )
#define IDB_OBM5_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 30 )
#define IDB_OBM6_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 31 )
#define IDB_OBM7_CONTROL_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 32 )
#define IDB_OBM0_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 33 )
#define IDB_OBM1_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 34 )
#define IDB_OBM2_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 35 )
#define IDB_OBM3_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 36 )
#define IDB_OBM4_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 37 )
#define IDB_OBM5_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 38 )
#define IDB_OBM6_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 39 )
#define IDB_OBM7_CA_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 40 )
#define IDB_OBM0_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 41 )
#define IDB_OBM1_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 42 )
#define IDB_OBM2_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 43 )
#define IDB_OBM3_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 44 )
#define IDB_OBM4_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 45 )
#define IDB_OBM5_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 46 )
#define IDB_OBM6_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 47 )
#define IDB_OBM7_CA_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 48 )
#define IDB_OBM0_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 49 )
#define IDB_OBM1_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 50 )
#define IDB_OBM2_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 51 )
#define IDB_OBM3_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 52 )
#define IDB_OBM4_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 53 )
#define IDB_OBM5_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 54 )
#define IDB_OBM6_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 55 )
#define IDB_OBM7_CA_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 56 )
#define IDB_OBM0_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 57 )
#define IDB_OBM1_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 58 )
#define IDB_OBM2_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 59 )
#define IDB_OBM3_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 60 )
#define IDB_OBM4_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 61 )
#define IDB_OBM5_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 62 )
#define IDB_OBM6_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 63 )
#define IDB_OBM7_CA_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 64 )
#define IDB_CA_CPU_CONTROL_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 65 )
#define IDB_CA_CPU_CONTROL_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 66 )
#define IDB_CA_CPU_CONTROL_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 67 )
#define IDB_CA_CPU_CONTROL_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 68 )
#define IDB_CA_LPBK_CONTROL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 69 )
#define IDB_CA_LPBK_CONTROL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 70 )
#define IDB_CA_LPBK_CONTROL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 71 )
#define IDB_CA_LPBK_CONTROL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 72 )
#define IDB_OBM0_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 73 )
#define IDB_OBM1_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 74 )
#define IDB_OBM2_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 75 )
#define IDB_OBM3_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 76 )
#define IDB_OBM4_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 77 )
#define IDB_OBM5_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 78 )
#define IDB_OBM6_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 79 )
#define IDB_OBM7_MAX_USAGE_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 80 )
#define IDB_OBM0_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 81 )
#define IDB_OBM1_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 82 )
#define IDB_OBM2_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 83 )
#define IDB_OBM3_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 84 )
#define IDB_OBM4_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 85 )
#define IDB_OBM5_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 86 )
#define IDB_OBM6_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 87 )
#define IDB_OBM7_MAX_USAGE_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 88 )
#define IDB_OBM0_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 89 )
#define IDB_OBM1_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 90 )
#define IDB_OBM2_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 91 )
#define IDB_OBM3_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 92 )
#define IDB_OBM4_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 93 )
#define IDB_OBM5_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 94 )
#define IDB_OBM6_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 95 )
#define IDB_OBM7_MAX_USAGE_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 96 )
#define IDB_OBM0_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 97 )
#define IDB_OBM1_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 98 )
#define IDB_OBM2_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 99 )
#define IDB_OBM3_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 100)
#define IDB_OBM4_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 101)
#define IDB_OBM5_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 102)
#define IDB_OBM6_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 103)
#define IDB_OBM7_MAX_USAGE_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 104)
#define IDB_OBM0_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 105)
#define IDB_OBM1_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 106)
#define IDB_OBM2_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 107)
#define IDB_OBM3_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 108)
#define IDB_OBM4_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 109)
#define IDB_OBM5_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 110)
#define IDB_OBM6_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 111)
#define IDB_OBM7_SHARED_CONFIG_PIPE0r          (BCM56960_A0_IP_EXTRA_REG_BASE + 112)
#define IDB_OBM0_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 113)
#define IDB_OBM1_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 114)
#define IDB_OBM2_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 115)
#define IDB_OBM3_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 116)
#define IDB_OBM4_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 117)
#define IDB_OBM5_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 118)
#define IDB_OBM6_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 119)
#define IDB_OBM7_SHARED_CONFIG_PIPE1r          (BCM56960_A0_IP_EXTRA_REG_BASE + 120)
#define IDB_OBM0_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 121)
#define IDB_OBM1_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 122)
#define IDB_OBM2_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 123)
#define IDB_OBM3_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 124)
#define IDB_OBM4_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 125)
#define IDB_OBM5_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 126)
#define IDB_OBM6_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 127)
#define IDB_OBM7_SHARED_CONFIG_PIPE2r          (BCM56960_A0_IP_EXTRA_REG_BASE + 128)
#define IDB_OBM0_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 129)
#define IDB_OBM1_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 130)
#define IDB_OBM2_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 131)
#define IDB_OBM3_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 132)
#define IDB_OBM4_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 133)
#define IDB_OBM5_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 134)
#define IDB_OBM6_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 135)
#define IDB_OBM7_SHARED_CONFIG_PIPE3r          (BCM56960_A0_IP_EXTRA_REG_BASE + 136)
#define IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 137)
#define IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 138)
#define IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 139)
#define IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 140)
#define IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 141)
#define IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 142)
#define IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 143)
#define IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE0r    (BCM56960_A0_IP_EXTRA_REG_BASE + 144)
#define IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 145)
#define IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 146)
#define IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 147)
#define IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 148)
#define IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 149)
#define IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 150)
#define IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 151)
#define IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE1r    (BCM56960_A0_IP_EXTRA_REG_BASE + 152)
#define IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 153)
#define IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 154)
#define IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 155)
#define IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 156)
#define IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 157)
#define IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 158)
#define IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 159)
#define IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE2r    (BCM56960_A0_IP_EXTRA_REG_BASE + 160)
#define IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 161)
#define IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 162)
#define IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 163)
#define IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 164)
#define IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 165)
#define IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 166)
#define IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 167)
#define IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE3r    (BCM56960_A0_IP_EXTRA_REG_BASE + 168)
#define IDB_OBM0_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 169)
#define IDB_OBM1_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 170)
#define IDB_OBM2_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 171)
#define IDB_OBM3_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 172)
#define IDB_OBM4_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 173)
#define IDB_OBM5_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 174)
#define IDB_OBM6_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 175)
#define IDB_OBM7_THRESHOLD_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 176)
#define IDB_OBM0_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 177)
#define IDB_OBM1_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 178)
#define IDB_OBM2_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 179)
#define IDB_OBM3_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 180)
#define IDB_OBM4_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 181)
#define IDB_OBM5_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 182)
#define IDB_OBM6_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 183)
#define IDB_OBM7_THRESHOLD_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 184)
#define IDB_OBM0_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 185)
#define IDB_OBM1_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 186)
#define IDB_OBM2_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 187)
#define IDB_OBM3_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 188)
#define IDB_OBM4_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 189)
#define IDB_OBM5_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 190)
#define IDB_OBM6_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 191)
#define IDB_OBM7_THRESHOLD_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 192)
#define IDB_OBM0_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 193)
#define IDB_OBM1_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 194)
#define IDB_OBM2_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 195)
#define IDB_OBM3_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 196)
#define IDB_OBM4_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 197)
#define IDB_OBM5_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 198)
#define IDB_OBM6_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 199)
#define IDB_OBM7_THRESHOLD_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 200)
#define IDB_OBM0_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 201)
#define IDB_OBM1_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 202)
#define IDB_OBM2_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 203)
#define IDB_OBM3_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 204)
#define IDB_OBM4_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 205)
#define IDB_OBM5_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 206)
#define IDB_OBM6_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 207)
#define IDB_OBM7_FC_THRESHOLD_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 208)
#define IDB_OBM0_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 209)
#define IDB_OBM1_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 210)
#define IDB_OBM2_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 211)
#define IDB_OBM3_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 212)
#define IDB_OBM4_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 213)
#define IDB_OBM5_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 214)
#define IDB_OBM6_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 215)
#define IDB_OBM7_FC_THRESHOLD_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 216)
#define IDB_OBM0_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 217)
#define IDB_OBM1_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 218)
#define IDB_OBM2_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 219)
#define IDB_OBM3_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 220)
#define IDB_OBM4_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 221)
#define IDB_OBM5_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 222)
#define IDB_OBM6_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 223)
#define IDB_OBM7_FC_THRESHOLD_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 224)
#define IDB_OBM0_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 225)
#define IDB_OBM1_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 226)
#define IDB_OBM2_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 227)
#define IDB_OBM3_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 228)
#define IDB_OBM4_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 229)
#define IDB_OBM5_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 230)
#define IDB_OBM6_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 231)
#define IDB_OBM7_FC_THRESHOLD_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 232)
#define IDB_OBM0_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 233)
#define IDB_OBM1_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 234)
#define IDB_OBM2_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 235)
#define IDB_OBM3_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 236)
#define IDB_OBM4_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 237)
#define IDB_OBM5_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 238)
#define IDB_OBM6_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 239)
#define IDB_OBM7_USAGE_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 240)
#define IDB_OBM0_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 241)
#define IDB_OBM1_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 242)
#define IDB_OBM2_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 243)
#define IDB_OBM3_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 244)
#define IDB_OBM4_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 245)
#define IDB_OBM5_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 246)
#define IDB_OBM6_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 247)
#define IDB_OBM7_USAGE_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 248)
#define IDB_OBM0_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 249)
#define IDB_OBM1_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 250)
#define IDB_OBM2_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 251)
#define IDB_OBM3_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 252)
#define IDB_OBM4_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 253)
#define IDB_OBM5_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 254)
#define IDB_OBM6_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 255)
#define IDB_OBM7_USAGE_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 256)
#define IDB_OBM0_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 257)
#define IDB_OBM1_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 258)
#define IDB_OBM2_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 259)
#define IDB_OBM3_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 260)
#define IDB_OBM4_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 261)
#define IDB_OBM5_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 262)
#define IDB_OBM6_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 263)
#define IDB_OBM7_USAGE_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 264)
#define IDB_OBM0_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 265)
#define IDB_OBM1_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 266)
#define IDB_OBM2_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 267)
#define IDB_OBM3_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 268)
#define IDB_OBM4_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 269)
#define IDB_OBM5_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 270)
#define IDB_OBM6_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 271)
#define IDB_OBM7_CA_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 272)
#define IDB_OBM0_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 273)
#define IDB_OBM1_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 274)
#define IDB_OBM2_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 275)
#define IDB_OBM3_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 276)
#define IDB_OBM4_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 277)
#define IDB_OBM5_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 278)
#define IDB_OBM6_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 279)
#define IDB_OBM7_CA_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 280)
#define IDB_OBM0_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 281)
#define IDB_OBM1_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 282)
#define IDB_OBM2_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 283)
#define IDB_OBM3_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 284)
#define IDB_OBM4_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 285)
#define IDB_OBM5_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 286)
#define IDB_OBM6_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 287)
#define IDB_OBM7_CA_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 288)
#define IDB_OBM0_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 289)
#define IDB_OBM1_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 290)
#define IDB_OBM2_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 291)
#define IDB_OBM3_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 292)
#define IDB_OBM4_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 293)
#define IDB_OBM5_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 294)
#define IDB_OBM6_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 295)
#define IDB_OBM7_CA_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 296)
#define IDB_OBM0_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 297)
#define IDB_OBM1_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 298)
#define IDB_OBM2_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 299)
#define IDB_OBM3_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 300)
#define IDB_OBM4_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 301)
#define IDB_OBM5_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 302)
#define IDB_OBM6_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 303)
#define IDB_OBM7_PORT_CONFIG_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 304)
#define IDB_OBM0_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 305)
#define IDB_OBM1_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 306)
#define IDB_OBM2_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 307)
#define IDB_OBM3_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 308)
#define IDB_OBM4_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 309)
#define IDB_OBM5_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 310)
#define IDB_OBM6_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 311)
#define IDB_OBM7_PORT_CONFIG_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 312)
#define IDB_OBM0_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 313)
#define IDB_OBM1_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 314)
#define IDB_OBM2_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 315)
#define IDB_OBM3_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 316)
#define IDB_OBM4_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 317)
#define IDB_OBM5_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 318)
#define IDB_OBM6_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 319)
#define IDB_OBM7_PORT_CONFIG_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 320)
#define IDB_OBM0_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 321)
#define IDB_OBM1_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 322)
#define IDB_OBM2_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 323)
#define IDB_OBM3_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 324)
#define IDB_OBM4_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 325)
#define IDB_OBM5_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 326)
#define IDB_OBM6_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 327)
#define IDB_OBM7_PORT_CONFIG_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 328)
#define IDB_OBM0_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 329)
#define IDB_OBM1_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 330)
#define IDB_OBM2_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 331)
#define IDB_OBM3_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 332)
#define IDB_OBM4_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 333)
#define IDB_OBM5_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 334)
#define IDB_OBM6_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 335)
#define IDB_OBM7_DBG_A_PIPE0r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 336)
#define IDB_OBM0_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 337)
#define IDB_OBM1_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 338)
#define IDB_OBM2_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 339)
#define IDB_OBM3_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 340)
#define IDB_OBM4_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 341)
#define IDB_OBM5_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 342)
#define IDB_OBM6_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 343)
#define IDB_OBM7_DBG_A_PIPE1r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 344)
#define IDB_OBM0_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 345)
#define IDB_OBM1_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 346)
#define IDB_OBM2_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 347)
#define IDB_OBM3_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 348)
#define IDB_OBM4_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 349)
#define IDB_OBM5_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 350)
#define IDB_OBM6_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 351)
#define IDB_OBM7_DBG_A_PIPE2r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 352)
#define IDB_OBM0_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 353)
#define IDB_OBM1_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 354)
#define IDB_OBM2_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 355)
#define IDB_OBM3_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 356)
#define IDB_OBM4_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 357)
#define IDB_OBM5_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 358)
#define IDB_OBM6_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 359)
#define IDB_OBM7_DBG_A_PIPE3r                  (BCM56960_A0_IP_EXTRA_REG_BASE + 360)
#define IDB_CA_CPU_HW_STATUS_PIPE0r            (BCM56960_A0_IP_EXTRA_REG_BASE + 361)
#define IDB_CA_CPU_HW_STATUS_PIPE1r            (BCM56960_A0_IP_EXTRA_REG_BASE + 362)
#define IDB_CA_CPU_HW_STATUS_PIPE2r            (BCM56960_A0_IP_EXTRA_REG_BASE + 363)
#define IDB_CA_CPU_HW_STATUS_PIPE3r            (BCM56960_A0_IP_EXTRA_REG_BASE + 364)
#define IDB_CA_LPBK_HW_STATUS_PIPE0r           (BCM56960_A0_IP_EXTRA_REG_BASE + 365)
#define IDB_CA_LPBK_HW_STATUS_PIPE1r           (BCM56960_A0_IP_EXTRA_REG_BASE + 366)
#define IDB_CA_LPBK_HW_STATUS_PIPE2r           (BCM56960_A0_IP_EXTRA_REG_BASE + 367)
#define IDB_CA_LPBK_HW_STATUS_PIPE3r           (BCM56960_A0_IP_EXTRA_REG_BASE + 368)
#define IDB_DBG_B_PIPE0r                       (BCM56960_A0_IP_EXTRA_REG_BASE + 369)
#define IDB_DBG_B_PIPE1r                       (BCM56960_A0_IP_EXTRA_REG_BASE + 370)
#define IDB_DBG_B_PIPE2r                       (BCM56960_A0_IP_EXTRA_REG_BASE + 371)
#define IDB_DBG_B_PIPE3r                       (BCM56960_A0_IP_EXTRA_REG_BASE + 372)

#define IS_PBLK0_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 373)
#define IS_PBLK0_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 374)
#define IS_PBLK0_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 375)
#define IS_PBLK0_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 376)
#define IS_PBLK1_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 377)
#define IS_PBLK1_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 378)
#define IS_PBLK1_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 379)
#define IS_PBLK1_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 380)
#define IS_PBLK2_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 381)
#define IS_PBLK2_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 382)
#define IS_PBLK2_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 383)
#define IS_PBLK2_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 384)
#define IS_PBLK3_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 385)
#define IS_PBLK3_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 386)
#define IS_PBLK3_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 387)
#define IS_PBLK3_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 388)
#define IS_PBLK4_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 389)
#define IS_PBLK4_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 390)
#define IS_PBLK4_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 391)
#define IS_PBLK4_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 392)
#define IS_PBLK5_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 393)
#define IS_PBLK5_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 394)
#define IS_PBLK5_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 395)
#define IS_PBLK5_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 396)
#define IS_PBLK6_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 397)
#define IS_PBLK6_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 398)
#define IS_PBLK6_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 399)
#define IS_PBLK6_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 400)
#define IS_PBLK7_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 401)
#define IS_PBLK7_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 402)
#define IS_PBLK7_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 403)
#define IS_PBLK7_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 404)

#define IS_HPIPE1_PBLK0_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 404)
#define IS_HPIPE1_PBLK0_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 405)
#define IS_HPIPE1_PBLK0_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 406)
#define IS_HPIPE1_PBLK0_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 407)
#define IS_HPIPE1_PBLK1_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 408)
#define IS_HPIPE1_PBLK1_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 409)
#define IS_HPIPE1_PBLK1_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 410)
#define IS_HPIPE1_PBLK1_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 411)
#define IS_HPIPE1_PBLK2_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 412)
#define IS_HPIPE1_PBLK2_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 413)
#define IS_HPIPE1_PBLK2_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 414)
#define IS_HPIPE1_PBLK2_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 415)
#define IS_HPIPE1_PBLK3_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 416)
#define IS_HPIPE1_PBLK3_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 417)
#define IS_HPIPE1_PBLK3_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 418)
#define IS_HPIPE1_PBLK3_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 419)
#define IS_HPIPE1_PBLK4_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 420)
#define IS_HPIPE1_PBLK4_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 421)
#define IS_HPIPE1_PBLK4_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 422)
#define IS_HPIPE1_PBLK4_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 423)
#define IS_HPIPE1_PBLK5_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 424)
#define IS_HPIPE1_PBLK5_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 425)
#define IS_HPIPE1_PBLK5_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 426)
#define IS_HPIPE1_PBLK5_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 427)
#define IS_HPIPE1_PBLK6_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 428)
#define IS_HPIPE1_PBLK6_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 429)
#define IS_HPIPE1_PBLK6_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 430)
#define IS_HPIPE1_PBLK6_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 431)
#define IS_HPIPE1_PBLK7_CALENDAR_PIPE0r        (BCM56960_A0_IP_EXTRA_REG_BASE + 432)
#define IS_HPIPE1_PBLK7_CALENDAR_PIPE1r        (BCM56960_A0_IP_EXTRA_REG_BASE + 433)
#define IS_HPIPE1_PBLK7_CALENDAR_PIPE2r        (BCM56960_A0_IP_EXTRA_REG_BASE + 434)
#define IS_HPIPE1_PBLK7_CALENDAR_PIPE3r        (BCM56960_A0_IP_EXTRA_REG_BASE + 435)

#define IS_TDM_CONFIG_PIPE0r                   (BCM56960_A0_IP_EXTRA_REG_BASE + 436)
#define IS_TDM_CONFIG_PIPE1r                   (BCM56960_A0_IP_EXTRA_REG_BASE + 437)
#define IS_TDM_CONFIG_PIPE2r                   (BCM56960_A0_IP_EXTRA_REG_BASE + 438)
#define IS_TDM_CONFIG_PIPE3r                   (BCM56960_A0_IP_EXTRA_REG_BASE + 439)

#define IS_OVR_SUB_GRP_CFG_PIPE0r              (BCM56960_A0_IP_EXTRA_REG_BASE + 440)
#define IS_OVR_SUB_GRP_CFG_PIPE1r              (BCM56960_A0_IP_EXTRA_REG_BASE + 441)
#define IS_OVR_SUB_GRP_CFG_PIPE2r              (BCM56960_A0_IP_EXTRA_REG_BASE + 442)
#define IS_OVR_SUB_GRP_CFG_PIPE3r              (BCM56960_A0_IP_EXTRA_REG_BASE + 443)

#define IS_OVR_SUB_GRP0_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 444)
#define IS_OVR_SUB_GRP0_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 445)
#define IS_OVR_SUB_GRP0_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 446)
#define IS_OVR_SUB_GRP0_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 447)

#define IS_OVR_SUB_GRP1_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 448)
#define IS_OVR_SUB_GRP1_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 449)
#define IS_OVR_SUB_GRP1_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 450)
#define IS_OVR_SUB_GRP1_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 451)

#define IS_OVR_SUB_GRP2_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 452)
#define IS_OVR_SUB_GRP2_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 453)
#define IS_OVR_SUB_GRP2_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 454)
#define IS_OVR_SUB_GRP2_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 455)

#define IS_OVR_SUB_GRP3_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 456)
#define IS_OVR_SUB_GRP3_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 457)
#define IS_OVR_SUB_GRP3_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 458)
#define IS_OVR_SUB_GRP3_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 459)

#define IS_OVR_SUB_GRP4_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 460)
#define IS_OVR_SUB_GRP4_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 461)
#define IS_OVR_SUB_GRP4_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 462)
#define IS_OVR_SUB_GRP4_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 463)

#define IS_OVR_SUB_GRP5_TBL_PIPE0r             (BCM56960_A0_IP_EXTRA_REG_BASE + 464)
#define IS_OVR_SUB_GRP5_TBL_PIPE1r             (BCM56960_A0_IP_EXTRA_REG_BASE + 465)
#define IS_OVR_SUB_GRP5_TBL_PIPE2r             (BCM56960_A0_IP_EXTRA_REG_BASE + 466)
#define IS_OVR_SUB_GRP5_TBL_PIPE3r             (BCM56960_A0_IP_EXTRA_REG_BASE + 467)

#define IS_CPU_LB_OPP_CFG_PIPE0r               (BCM56960_A0_IP_EXTRA_REG_BASE + 468)
#define IS_CPU_LB_OPP_CFG_PIPE1r               (BCM56960_A0_IP_EXTRA_REG_BASE + 469)
#define IS_CPU_LB_OPP_CFG_PIPE2r               (BCM56960_A0_IP_EXTRA_REG_BASE + 470)
#define IS_CPU_LB_OPP_CFG_PIPE3r               (BCM56960_A0_IP_EXTRA_REG_BASE + 471)


#define IS_OPP_SCHED_CFG_PIPE0r                (BCM56960_A0_IP_EXTRA_REG_BASE + 472)
#define IS_OPP_SCHED_CFG_PIPE1r                (BCM56960_A0_IP_EXTRA_REG_BASE + 473)
#define IS_OPP_SCHED_CFG_PIPE2r                (BCM56960_A0_IP_EXTRA_REG_BASE + 474)
#define IS_OPP_SCHED_CFG_PIPE3r                (BCM56960_A0_IP_EXTRA_REG_BASE + 475)

#define IS_TDM_HSP_PIPE0r                      (BCM56960_A0_IP_EXTRA_REG_BASE + 476)
#define IS_TDM_HSP_PIPE1r                      (BCM56960_A0_IP_EXTRA_REG_BASE + 477)
#define IS_TDM_HSP_PIPE2r                      (BCM56960_A0_IP_EXTRA_REG_BASE + 478)
#define IS_TDM_HSP_PIPE3r                      (BCM56960_A0_IP_EXTRA_REG_BASE + 479)





/* EPIPE Registers */
#define EGR_EDB_MISC_CTRL_PIPE0r                (BCM56960_A0_EP_EXTRA_REG_BASE +  1)
#define EGR_EDB_MISC_CTRL_PIPE1r                (BCM56960_A0_EP_EXTRA_REG_BASE +  2)
#define EGR_EDB_MISC_CTRL_PIPE2r                (BCM56960_A0_EP_EXTRA_REG_BASE +  3)
#define EGR_EDB_MISC_CTRL_PIPE3r                (BCM56960_A0_EP_EXTRA_REG_BASE +  4)

#define EGR_FLEXPORT_EXTRA_HOLDING_PIPE0r       (BCM56960_A0_EP_EXTRA_REG_BASE +  5)
#define EGR_FLEXPORT_EXTRA_HOLDING_PIPE1r       (BCM56960_A0_EP_EXTRA_REG_BASE +  6)
#define EGR_FLEXPORT_EXTRA_HOLDING_PIPE2r       (BCM56960_A0_EP_EXTRA_REG_BASE +  7)
#define EGR_FLEXPORT_EXTRA_HOLDING_PIPE3r       (BCM56960_A0_EP_EXTRA_REG_BASE +  8)

#define EGR_PORT_BUFFER_SFT_RESET_0_PIPE0r      (BCM56960_A0_EP_EXTRA_REG_BASE +  9)
#define EGR_PORT_BUFFER_SFT_RESET_0_PIPE1r      (BCM56960_A0_EP_EXTRA_REG_BASE + 10)
#define EGR_PORT_BUFFER_SFT_RESET_0_PIPE2r      (BCM56960_A0_EP_EXTRA_REG_BASE + 11)
#define EGR_PORT_BUFFER_SFT_RESET_0_PIPE3r      (BCM56960_A0_EP_EXTRA_REG_BASE + 12)

#define EGR_DEVICE_TO_PHYSICAL_PORT_NUMBER_MAPPINGr (BCM56960_A0_EP_EXTRA_REG_BASE + 13)
#define MMU_PORT_TO_DEVICE_PORT_MAPPINGr        (BCM56960_A0_EP_EXTRA_REG_BASE + 14)
#define MMU_PORT_TO_PHY_PORT_MAPPINGr           (BCM56960_A0_EP_EXTRA_REG_BASE + 15)




/* MMU Registers */
#define CT_PURGE_CNT_XPE0r                                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 1  )
#define CT_PURGE_CNT_XPE1r                                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 2  )
#define CT_PURGE_CNT_XPE2r                                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 3  )
#define CT_PURGE_CNT_XPE3r                                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 4  )
#define MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 5  )
#define MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 6  )
#define MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 7  )
#define MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 8  )
#define MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE0r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 9  )
#define MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE1r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 10 )
#define MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE2r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 11 )
#define MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE3r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 12 )
#define MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 13 )
#define MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 14 )
#define MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 15 )
#define MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 16 )
#define MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 17 )
#define MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 18 )
#define MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 19 )
#define MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 20 )
#define MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 21 )
#define MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 22 )
#define MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 23 )
#define MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 24 )
#define MMU_THDM_DB_POOL_RESUME_LIMIT_XPE0r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 25 )
#define MMU_THDM_DB_POOL_RESUME_LIMIT_XPE1r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 26 )
#define MMU_THDM_DB_POOL_RESUME_LIMIT_XPE2r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 27 )
#define MMU_THDM_DB_POOL_RESUME_LIMIT_XPE3r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 28 )
#define MMU_THDM_DB_POOL_SHARED_LIMIT_XPE0r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 29 )
#define MMU_THDM_DB_POOL_SHARED_LIMIT_XPE1r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 30 )
#define MMU_THDM_DB_POOL_SHARED_LIMIT_XPE2r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 31 )
#define MMU_THDM_DB_POOL_SHARED_LIMIT_XPE3r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 32 )
#define MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE0r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 33 )
#define MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE1r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 34 )
#define MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE2r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 35 )
#define MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE3r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 36 )
#define MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE0r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 37 )
#define MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE1r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 38 )
#define MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE2r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 39 )
#define MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE3r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 40 )
#define MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE0r                   (BCM56960_A0_MMU_EXTRA_REG_BASE + 41 )
#define MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE1r                   (BCM56960_A0_MMU_EXTRA_REG_BASE + 42 )
#define MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE2r                   (BCM56960_A0_MMU_EXTRA_REG_BASE + 43 )
#define MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE3r                   (BCM56960_A0_MMU_EXTRA_REG_BASE + 44 )
#define MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE0r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 45 )
#define MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE1r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 46 )
#define MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE2r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 47 )
#define MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE3r               (BCM56960_A0_MMU_EXTRA_REG_BASE + 48 )
#define MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE0r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 49 )
#define MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE1r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 50 )
#define MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE2r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 51 )
#define MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE3r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 52 )
#define MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE0r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 53 )
#define MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE1r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 54 )
#define MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE2r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 55 )
#define MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE3r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 56 )
#define MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE0r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 57 )
#define MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE1r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 58 )
#define MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE2r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 59 )
#define MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE3r           (BCM56960_A0_MMU_EXTRA_REG_BASE + 60 )
#define MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE0r        (BCM56960_A0_MMU_EXTRA_REG_BASE + 61 )
#define MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE1r        (BCM56960_A0_MMU_EXTRA_REG_BASE + 62 )
#define MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE2r        (BCM56960_A0_MMU_EXTRA_REG_BASE + 63 )
#define MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE3r        (BCM56960_A0_MMU_EXTRA_REG_BASE + 64 )
#define MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 65 )
#define MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 66 )
#define MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 67 )
#define MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 68 )
#define MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 69 )
#define MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 70 )
#define MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 71 )
#define MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 72 )
#define MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE0r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 73 )
#define MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE1r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 74 )
#define MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE2r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 75 )
#define MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE3r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 76 )
#define MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE0r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 77 )
#define MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE1r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 78 )
#define MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE2r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 79 )
#define MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE3r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 80 )
#define MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE0r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 81 )
#define MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE1r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 82 )
#define MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE2r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 83 )
#define MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE3r                (BCM56960_A0_MMU_EXTRA_REG_BASE + 84 )
#define MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE0r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 85 )
#define MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE1r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 86 )
#define MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE2r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 87 )
#define MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE3r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 88 )
#define MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE0r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 89 )
#define MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE1r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 90 )
#define MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE2r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 91 )
#define MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE3r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 92 )
#define MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE0r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 93 )
#define MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE1r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 94 )
#define MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE2r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 95 )
#define MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE3r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 96 )
#define MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE0r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 97 )
#define MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE1r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 98 )
#define MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE2r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 99 )
#define MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE3r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 100)
#define MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE0r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 101)
#define MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE1r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 102)
#define MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE2r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 103)
#define MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE3r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 104)
#define MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE0r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 105)
#define MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE1r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 106)
#define MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE2r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 107)
#define MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE3r             (BCM56960_A0_MMU_EXTRA_REG_BASE + 108)
#define MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE0r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 109)
#define MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE1r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 110)
#define MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE2r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 111)
#define MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE3r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 112)
#define MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 113)
#define MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 114)
#define MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 115)
#define MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 116)
#define MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE0r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 117)
#define MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE1r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 118)
#define MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE2r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 119)
#define MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE3r         (BCM56960_A0_MMU_EXTRA_REG_BASE + 120)
#define MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE0r     (BCM56960_A0_MMU_EXTRA_REG_BASE + 121)
#define MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE1r     (BCM56960_A0_MMU_EXTRA_REG_BASE + 122)
#define MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE2r     (BCM56960_A0_MMU_EXTRA_REG_BASE + 123)
#define MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE3r     (BCM56960_A0_MMU_EXTRA_REG_BASE + 124)
#define MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 125)
#define MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 126)
#define MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 127)
#define MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3r       (BCM56960_A0_MMU_EXTRA_REG_BASE + 128)
#define MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE0r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 129)
#define MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE1r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 130)
#define MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE2r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 131)
#define MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE3r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 132)
#define MMU_THDR_DB_BST_THRESHOLD_SP_XPE0r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 133)
#define MMU_THDR_DB_BST_THRESHOLD_SP_XPE1r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 134)
#define MMU_THDR_DB_BST_THRESHOLD_SP_XPE2r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 135)
#define MMU_THDR_DB_BST_THRESHOLD_SP_XPE3r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 136)
#define MMU_THDR_DB_CONFIG_SP_XPE0r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 137)
#define MMU_THDR_DB_CONFIG_SP_XPE1r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 138)
#define MMU_THDR_DB_CONFIG_SP_XPE2r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 139)
#define MMU_THDR_DB_CONFIG_SP_XPE3r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 140)
#define MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 141)
#define MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 142)
#define MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 143)
#define MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 144)
#define MMU_THDR_DB_SP_SHARED_LIMIT_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 145)
#define MMU_THDR_DB_SP_SHARED_LIMIT_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 146)
#define MMU_THDR_DB_SP_SHARED_LIMIT_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 147)
#define MMU_THDR_DB_SP_SHARED_LIMIT_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 148)
#define OP_UC_PORT_DROP_STATE_XPE0r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 149)
#define OP_UC_PORT_DROP_STATE_XPE1r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 150)
#define OP_UC_PORT_DROP_STATE_XPE2r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 151)
#define OP_UC_PORT_DROP_STATE_XPE3r                              (BCM56960_A0_MMU_EXTRA_REG_BASE + 152)
#define OP_UC_PORT_RED_DROP_STATE_XPE0r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 153)
#define OP_UC_PORT_RED_DROP_STATE_XPE1r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 154)
#define OP_UC_PORT_RED_DROP_STATE_XPE2r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 155)
#define OP_UC_PORT_RED_DROP_STATE_XPE3r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 156)
#define OP_UC_PORT_YELLOW_DROP_STATE_XPE0r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 157)
#define OP_UC_PORT_YELLOW_DROP_STATE_XPE1r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 158)
#define OP_UC_PORT_YELLOW_DROP_STATE_XPE2r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 159)
#define OP_UC_PORT_YELLOW_DROP_STATE_XPE3r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 160)
#define OP_UC_QGROUP_DROP_STATE_XPE0r                            (BCM56960_A0_MMU_EXTRA_REG_BASE + 161)
#define OP_UC_QGROUP_DROP_STATE_XPE1r                            (BCM56960_A0_MMU_EXTRA_REG_BASE + 162)
#define OP_UC_QGROUP_DROP_STATE_XPE2r                            (BCM56960_A0_MMU_EXTRA_REG_BASE + 163)
#define OP_UC_QGROUP_DROP_STATE_XPE3r                            (BCM56960_A0_MMU_EXTRA_REG_BASE + 164)
#define OP_UC_QGROUP_RED_DROP_STATE_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 165)
#define OP_UC_QGROUP_RED_DROP_STATE_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 166)
#define OP_UC_QGROUP_RED_DROP_STATE_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 167)
#define OP_UC_QGROUP_RED_DROP_STATE_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 168)
#define OP_UC_QGROUP_YELLOW_DROP_STATE_XPE0r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 169)
#define OP_UC_QGROUP_YELLOW_DROP_STATE_XPE1r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 170)
#define OP_UC_QGROUP_YELLOW_DROP_STATE_XPE2r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 171)
#define OP_UC_QGROUP_YELLOW_DROP_STATE_XPE3r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 172)
#define OP_UC_QUEUE_DROP_STATE_XPE0r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 173)
#define OP_UC_QUEUE_DROP_STATE_XPE1r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 174)
#define OP_UC_QUEUE_DROP_STATE_XPE2r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 175)
#define OP_UC_QUEUE_DROP_STATE_XPE3r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 176)
#define OP_UC_QUEUE_RED_DROP_STATE_XPE0r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 177)
#define OP_UC_QUEUE_RED_DROP_STATE_XPE1r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 178)
#define OP_UC_QUEUE_RED_DROP_STATE_XPE2r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 179)
#define OP_UC_QUEUE_RED_DROP_STATE_XPE3r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 180)
#define OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 181)
#define OP_UC_QUEUE_YELLOW_DROP_STATE_XPE1r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 182)
#define OP_UC_QUEUE_YELLOW_DROP_STATE_XPE2r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 183)
#define OP_UC_QUEUE_YELLOW_DROP_STATE_XPE3r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 184)
#define THDI_BST_PG_HDRM_PROFILE_XPE0r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 185)
#define THDI_BST_PG_HDRM_PROFILE_XPE1r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 186)
#define THDI_BST_PG_HDRM_PROFILE_XPE2r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 187)
#define THDI_BST_PG_HDRM_PROFILE_XPE3r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 188)
#define THDI_BST_PG_SHARED_PROFILE_XPE0r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 189)
#define THDI_BST_PG_SHARED_PROFILE_XPE1r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 190)
#define THDI_BST_PG_SHARED_PROFILE_XPE2r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 191)
#define THDI_BST_PG_SHARED_PROFILE_XPE3r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 192)
#define THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE0r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 193)
#define THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE1r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 194)
#define THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE2r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 195)
#define THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE3r                  (BCM56960_A0_MMU_EXTRA_REG_BASE + 196)
#define THDI_BST_SP_SHARED_PROFILE_XPE0r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 197)
#define THDI_BST_SP_SHARED_PROFILE_XPE1r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 198)
#define THDI_BST_SP_SHARED_PROFILE_XPE2r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 199)
#define THDI_BST_SP_SHARED_PROFILE_XPE3r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 200)
#define THDI_BST_TRIGGER_STATUS_32_XPE0r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 201)
#define THDI_BST_TRIGGER_STATUS_32_XPE1r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 202)
#define THDI_BST_TRIGGER_STATUS_32_XPE2r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 203)
#define THDI_BST_TRIGGER_STATUS_32_XPE3r                         (BCM56960_A0_MMU_EXTRA_REG_BASE + 204)
#define THDI_BST_TRIGGER_STATUS_TYPE_XPE0r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 205)
#define THDI_BST_TRIGGER_STATUS_TYPE_XPE1r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 206)
#define THDI_BST_TRIGGER_STATUS_TYPE_XPE2r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 207)
#define THDI_BST_TRIGGER_STATUS_TYPE_XPE3r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 208)
#define THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE0r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 209)
#define THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE1r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 210)
#define THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE2r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 211)
#define THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE3r                 (BCM56960_A0_MMU_EXTRA_REG_BASE + 212)
#define THDI_BUFFER_CELL_LIMIT_SP_XPE0r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 213)
#define THDI_BUFFER_CELL_LIMIT_SP_XPE1r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 214)
#define THDI_BUFFER_CELL_LIMIT_SP_XPE2r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 215)
#define THDI_BUFFER_CELL_LIMIT_SP_XPE3r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 216)
#define THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE0r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 217)
#define THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE1r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 218)
#define THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE2r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 219)
#define THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE3r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 220)
#define THDI_CELL_SPAP_RED_OFFSET_SP_XPE0r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 221)
#define THDI_CELL_SPAP_RED_OFFSET_SP_XPE1r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 222)
#define THDI_CELL_SPAP_RED_OFFSET_SP_XPE2r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 223)
#define THDI_CELL_SPAP_RED_OFFSET_SP_XPE3r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 224)
#define THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE0r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 225)
#define THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE1r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 226)
#define THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE2r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 227)
#define THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE3r                    (BCM56960_A0_MMU_EXTRA_REG_BASE + 228)
#define THDI_FLOW_CONTROL_XOFF_STATE_XPE0r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 229)
#define THDI_FLOW_CONTROL_XOFF_STATE_XPE1r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 230)
#define THDI_FLOW_CONTROL_XOFF_STATE_XPE2r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 231)
#define THDI_FLOW_CONTROL_XOFF_STATE_XPE3r                       (BCM56960_A0_MMU_EXTRA_REG_BASE + 232)
#define THDI_GLOBAL_HDRM_COUNT_XPE0r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 233)
#define THDI_GLOBAL_HDRM_COUNT_XPE1r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 234)
#define THDI_GLOBAL_HDRM_COUNT_XPE2r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 235)
#define THDI_GLOBAL_HDRM_COUNT_XPE3r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 236)
#define THDI_GLOBAL_HDRM_RESERVED_XPE0r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 237)
#define THDI_GLOBAL_HDRM_RESERVED_XPE1r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 238)
#define THDI_GLOBAL_HDRM_RESERVED_XPE2r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 239)
#define THDI_GLOBAL_HDRM_RESERVED_XPE3r                          (BCM56960_A0_MMU_EXTRA_REG_BASE + 240)
#define THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE0r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 241)
#define THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE1r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 242)
#define THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE2r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 243)
#define THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE3r                     (BCM56960_A0_MMU_EXTRA_REG_BASE + 244)
#define THDI_MEM_INIT_STATUS_XPE0r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 245)
#define THDI_MEM_INIT_STATUS_XPE1r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 246)
#define THDI_MEM_INIT_STATUS_XPE2r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 247)
#define THDI_MEM_INIT_STATUS_XPE3r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 248)
#define THDI_PORT_LIMIT_STATES_XPE0r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 249)
#define THDI_PORT_LIMIT_STATES_XPE1r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 250)
#define THDI_PORT_LIMIT_STATES_XPE2r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 251)
#define THDI_PORT_LIMIT_STATES_XPE3r                             (BCM56960_A0_MMU_EXTRA_REG_BASE + 252)
#define THDU_CNG_STATE_RESET_XPE0r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 253)
#define THDU_CNG_STATE_RESET_XPE1r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 254)
#define THDU_CNG_STATE_RESET_XPE2r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 255)
#define THDU_CNG_STATE_RESET_XPE3r                               (BCM56960_A0_MMU_EXTRA_REG_BASE + 256)
#define THDU_OUTPUT_PORT_RX_ENABLE_64_XPE0r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 257)
#define THDU_OUTPUT_PORT_RX_ENABLE_64_XPE1r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 258)
#define THDU_OUTPUT_PORT_RX_ENABLE_64_XPE2r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 259)
#define THDU_OUTPUT_PORT_RX_ENABLE_64_XPE3r                      (BCM56960_A0_MMU_EXTRA_REG_BASE + 260)
#define THDU_PORT_E2ECC_COS_SPID_XPE0r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 261)
#define THDU_PORT_E2ECC_COS_SPID_XPE1r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 262)
#define THDU_PORT_E2ECC_COS_SPID_XPE2r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 263)
#define THDU_PORT_E2ECC_COS_SPID_XPE3r                           (BCM56960_A0_MMU_EXTRA_REG_BASE + 264)
#define WRED_POOL_INST_CONG_LIMIT_0_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 265)
#define WRED_POOL_INST_CONG_LIMIT_0_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 266)
#define WRED_POOL_INST_CONG_LIMIT_0_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 267)
#define WRED_POOL_INST_CONG_LIMIT_0_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 268)
#define WRED_POOL_INST_CONG_LIMIT_1_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 269)
#define WRED_POOL_INST_CONG_LIMIT_1_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 270)
#define WRED_POOL_INST_CONG_LIMIT_1_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 271)
#define WRED_POOL_INST_CONG_LIMIT_1_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 272)
#define WRED_POOL_INST_CONG_LIMIT_2_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 273)
#define WRED_POOL_INST_CONG_LIMIT_2_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 274)
#define WRED_POOL_INST_CONG_LIMIT_2_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 275)
#define WRED_POOL_INST_CONG_LIMIT_2_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 276)
#define WRED_POOL_INST_CONG_LIMIT_3_XPE0r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 277)
#define WRED_POOL_INST_CONG_LIMIT_3_XPE1r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 278)
#define WRED_POOL_INST_CONG_LIMIT_3_XPE2r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 279)
#define WRED_POOL_INST_CONG_LIMIT_3_XPE3r                        (BCM56960_A0_MMU_EXTRA_REG_BASE + 280)


/* MMU Memories  */
#define MMU_CCP_RESEQ_MEM_XPE0_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 1  )
#define MMU_CCP_RESEQ_MEM_XPE0_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 2  )
#define MMU_CCP_RESEQ_MEM_XPE1_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 3  )
#define MMU_CCP_RESEQ_MEM_XPE1_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 4  )
#define MMU_CCP_RESEQ_MEM_XPE2_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 5  )
#define MMU_CCP_RESEQ_MEM_XPE2_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 6  )
#define MMU_CCP_RESEQ_MEM_XPE3_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 7  )
#define MMU_CCP_RESEQ_MEM_XPE3_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 8  )
#define MMU_CTR_MC_DROP_MEM_XPE0_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 9  )
#define MMU_CTR_MC_DROP_MEM_XPE0_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 10 )
#define MMU_CTR_MC_DROP_MEM_XPE1_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 11 )
#define MMU_CTR_MC_DROP_MEM_XPE1_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 12 )
#define MMU_CTR_MC_DROP_MEM_XPE2_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 13 )
#define MMU_CTR_MC_DROP_MEM_XPE2_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 14 )
#define MMU_CTR_MC_DROP_MEM_XPE3_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 15 )
#define MMU_CTR_MC_DROP_MEM_XPE3_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 16 )
#define MMU_CTR_UC_DROP_MEM_XPE0_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 17 )
#define MMU_CTR_UC_DROP_MEM_XPE0_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 18 )
#define MMU_CTR_UC_DROP_MEM_XPE1_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 19 )
#define MMU_CTR_UC_DROP_MEM_XPE1_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 20 )
#define MMU_CTR_UC_DROP_MEM_XPE2_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 21 )
#define MMU_CTR_UC_DROP_MEM_XPE2_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 22 )
#define MMU_CTR_UC_DROP_MEM_XPE3_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 23 )
#define MMU_CTR_UC_DROP_MEM_XPE3_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 24 )
#define MMU_CTR_WRED_DROP_MEM_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 25 )
#define MMU_CTR_WRED_DROP_MEM_XPE0_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 26 )
#define MMU_CTR_WRED_DROP_MEM_XPE1_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 27 )
#define MMU_CTR_WRED_DROP_MEM_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 28 )
#define MMU_CTR_WRED_DROP_MEM_XPE2_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 29 )
#define MMU_CTR_WRED_DROP_MEM_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 30 )
#define MMU_CTR_WRED_DROP_MEM_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 31 )
#define MMU_CTR_WRED_DROP_MEM_XPE3_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 32 )
#define MMU_ENQS_PBI_DB_SC0_PIPE0m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 33 )
#define MMU_ENQS_PBI_DB_SC0_PIPE1m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 34 )
#define MMU_ENQS_PBI_DB_SC0_PIPE2m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 35 )
#define MMU_ENQS_PBI_DB_SC0_PIPE3m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 36 )
#define MMU_ENQS_PBI_DB_SC1_PIPE0m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 37 )
#define MMU_ENQS_PBI_DB_SC1_PIPE1m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 38 )
#define MMU_ENQS_PBI_DB_SC1_PIPE2m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 39 )
#define MMU_ENQS_PBI_DB_SC1_PIPE3m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 40 )
#define MMU_ENQX_PIPEMEM_HI_XPE0_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 41 )
#define MMU_ENQX_PIPEMEM_HI_XPE0_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 42 )
#define MMU_ENQX_PIPEMEM_HI_XPE1_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 43 )
#define MMU_ENQX_PIPEMEM_HI_XPE1_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 44 )
#define MMU_ENQX_PIPEMEM_HI_XPE2_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 45 )
#define MMU_ENQX_PIPEMEM_HI_XPE2_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 46 )
#define MMU_ENQX_PIPEMEM_HI_XPE3_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 47 )
#define MMU_ENQX_PIPEMEM_HI_XPE3_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 48 )
#define MMU_ENQX_PIPEMEM_LO_XPE0_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 49 )
#define MMU_ENQX_PIPEMEM_LO_XPE0_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 50 )
#define MMU_ENQX_PIPEMEM_LO_XPE1_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 51 )
#define MMU_ENQX_PIPEMEM_LO_XPE1_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 52 )
#define MMU_ENQX_PIPEMEM_LO_XPE2_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 53 )
#define MMU_ENQX_PIPEMEM_LO_XPE2_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 54 )
#define MMU_ENQX_PIPEMEM_LO_XPE3_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 55 )
#define MMU_ENQX_PIPEMEM_LO_XPE3_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 56 )
#define MMU_EPRG_MEM_XPE0m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 57 )
#define MMU_EPRG_MEM_XPE1m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 58 )
#define MMU_EPRG_MEM_XPE2m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 59 )
#define MMU_EPRG_MEM_XPE3m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 60 )
#define MMU_PQE0_MEM_XPE0m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 61 )
#define MMU_PQE0_MEM_XPE1m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 62 )
#define MMU_PQE0_MEM_XPE2m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 63 )
#define MMU_PQE0_MEM_XPE3m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 64 )
#define MMU_PQE1_MEM_XPE0m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 65 )
#define MMU_PQE1_MEM_XPE1m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 66 )
#define MMU_PQE1_MEM_XPE2m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 67 )
#define MMU_PQE1_MEM_XPE3m                                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 68 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC0m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 69 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC1m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 70 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0m                 (BCM56960_A0_MMU_EXTRA_MEM_BASE + 71 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1m                 (BCM56960_A0_MMU_EXTRA_MEM_BASE + 72 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0m                 (BCM56960_A0_MMU_EXTRA_MEM_BASE + 73 )
#define MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1m                 (BCM56960_A0_MMU_EXTRA_MEM_BASE + 74 )
#define MMU_THDM_DB_PORTSP_BST_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 75 )
#define MMU_THDM_DB_PORTSP_BST_XPE0_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 76 )
#define MMU_THDM_DB_PORTSP_BST_XPE1_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 77 )
#define MMU_THDM_DB_PORTSP_BST_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 78 )
#define MMU_THDM_DB_PORTSP_BST_XPE2_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 79 )
#define MMU_THDM_DB_PORTSP_BST_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 80 )
#define MMU_THDM_DB_PORTSP_BST_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 81 )
#define MMU_THDM_DB_PORTSP_BST_XPE3_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 82 )
#define MMU_THDM_DB_PORTSP_CONFIG_PIPE0m                        (BCM56960_A0_MMU_EXTRA_MEM_BASE + 83 )
#define MMU_THDM_DB_PORTSP_CONFIG_PIPE1m                        (BCM56960_A0_MMU_EXTRA_MEM_BASE + 84 )
#define MMU_THDM_DB_PORTSP_CONFIG_PIPE2m                        (BCM56960_A0_MMU_EXTRA_MEM_BASE + 85 )
#define MMU_THDM_DB_PORTSP_CONFIG_PIPE3m                        (BCM56960_A0_MMU_EXTRA_MEM_BASE + 86 )
#define MMU_THDM_DB_PORTSP_CONFIG_A_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 87 )
#define MMU_THDM_DB_PORTSP_CONFIG_A_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 88 )
#define MMU_THDM_DB_PORTSP_CONFIG_A_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 89 )
#define MMU_THDM_DB_PORTSP_CONFIG_A_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 90 )
#define MMU_THDM_DB_PORTSP_CONFIG_B_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 91 )
#define MMU_THDM_DB_PORTSP_CONFIG_B_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 92 )
#define MMU_THDM_DB_PORTSP_CONFIG_B_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 93 )
#define MMU_THDM_DB_PORTSP_CONFIG_B_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 94 )
#define MMU_THDM_DB_PORTSP_CONFIG_C_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 95 )
#define MMU_THDM_DB_PORTSP_CONFIG_C_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 96 )
#define MMU_THDM_DB_PORTSP_CONFIG_C_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 97 )
#define MMU_THDM_DB_PORTSP_CONFIG_C_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 98 )
#define MMU_THDM_DB_QUEUE_BST_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 99 )
#define MMU_THDM_DB_QUEUE_BST_XPE0_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 100)
#define MMU_THDM_DB_QUEUE_BST_XPE1_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 101)
#define MMU_THDM_DB_QUEUE_BST_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 102)
#define MMU_THDM_DB_QUEUE_BST_XPE2_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 103)
#define MMU_THDM_DB_QUEUE_BST_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 104)
#define MMU_THDM_DB_QUEUE_BST_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 105)
#define MMU_THDM_DB_QUEUE_BST_XPE3_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 106)
#define MMU_THDM_DB_QUEUE_CONFIG_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 107)
#define MMU_THDM_DB_QUEUE_CONFIG_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 108)
#define MMU_THDM_DB_QUEUE_CONFIG_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 109)
#define MMU_THDM_DB_QUEUE_CONFIG_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 110)
#define MMU_THDM_DB_QUEUE_CONFIG_A_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 111)
#define MMU_THDM_DB_QUEUE_CONFIG_A_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 112)
#define MMU_THDM_DB_QUEUE_CONFIG_A_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 113)
#define MMU_THDM_DB_QUEUE_CONFIG_A_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 114)
#define MMU_THDM_DB_QUEUE_CONFIG_B_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 115)
#define MMU_THDM_DB_QUEUE_CONFIG_B_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 116)
#define MMU_THDM_DB_QUEUE_CONFIG_B_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 117)
#define MMU_THDM_DB_QUEUE_CONFIG_B_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 118)
#define MMU_THDM_DB_QUEUE_CONFIG_C_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 119)
#define MMU_THDM_DB_QUEUE_CONFIG_C_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 120)
#define MMU_THDM_DB_QUEUE_CONFIG_C_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 121)
#define MMU_THDM_DB_QUEUE_CONFIG_C_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 122)
#define MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 123)
#define MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 124)
#define MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 125)
#define MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 126)
#define MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 127)
#define MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 128)
#define MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 129)
#define MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 130)
#define MMU_THDM_DB_QUEUE_OFFSET_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 131)
#define MMU_THDM_DB_QUEUE_OFFSET_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 132)
#define MMU_THDM_DB_QUEUE_OFFSET_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 133)
#define MMU_THDM_DB_QUEUE_OFFSET_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 134)
#define MMU_THDM_DB_QUEUE_OFFSET_A_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 135)
#define MMU_THDM_DB_QUEUE_OFFSET_A_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 136)
#define MMU_THDM_DB_QUEUE_OFFSET_A_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 137)
#define MMU_THDM_DB_QUEUE_OFFSET_A_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 138)
#define MMU_THDM_DB_QUEUE_OFFSET_B_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 139)
#define MMU_THDM_DB_QUEUE_OFFSET_B_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 140)
#define MMU_THDM_DB_QUEUE_OFFSET_B_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 141)
#define MMU_THDM_DB_QUEUE_OFFSET_B_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 142)
#define MMU_THDM_DB_QUEUE_OFFSET_C_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 143)
#define MMU_THDM_DB_QUEUE_OFFSET_C_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 144)
#define MMU_THDM_DB_QUEUE_OFFSET_C_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 145)
#define MMU_THDM_DB_QUEUE_OFFSET_C_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 146)
#define MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 147)
#define MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 148)
#define MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 149)
#define MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 150)
#define MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 151)
#define MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 152)
#define MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 153)
#define MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 154)
#define MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 155)
#define MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 156)
#define MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 157)
#define MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 158)
#define MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 159)
#define MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 160)
#define MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 161)
#define MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 162)
#define MMU_THDM_MCQE_PORTSP_CONFIG_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 163)
#define MMU_THDM_MCQE_PORTSP_CONFIG_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 164)
#define MMU_THDM_MCQE_PORTSP_CONFIG_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 165)
#define MMU_THDM_MCQE_PORTSP_CONFIG_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 166)
#define MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 167)
#define MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 168)
#define MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 169)
#define MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 170)
#define MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 171)
#define MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 172)
#define MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 173)
#define MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 174)
#define MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE0m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 175)
#define MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE1m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 176)
#define MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE2m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 177)
#define MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE3m                    (BCM56960_A0_MMU_EXTRA_MEM_BASE + 178)
#define MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 179)
#define MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 180)
#define MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 181)
#define MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 182)
#define MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 183)
#define MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 184)
#define MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 185)
#define MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 186)
#define MMU_THDM_MCQE_QUEUE_CONFIG_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 187)
#define MMU_THDM_MCQE_QUEUE_CONFIG_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 188)
#define MMU_THDM_MCQE_QUEUE_CONFIG_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 189)
#define MMU_THDM_MCQE_QUEUE_CONFIG_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 190)
#define MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 191)
#define MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 192)
#define MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 193)
#define MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 194)
#define MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 195)
#define MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 196)
#define MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 197)
#define MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 198)
#define MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 199)
#define MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 200)
#define MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 201)
#define MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 202)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE0m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 203)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE1m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 204)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE2m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 205)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE3m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 206)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE0m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 207)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE1m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 208)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE2m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 209)
#define MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE3m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 210)
#define MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 211)
#define MMU_THDM_MCQE_QUEUE_OFFSET_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 212)
#define MMU_THDM_MCQE_QUEUE_OFFSET_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 213)
#define MMU_THDM_MCQE_QUEUE_OFFSET_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 214)
#define MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 215)
#define MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 216)
#define MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 217)
#define MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 218)
#define MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 219)
#define MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 220)
#define MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 221)
#define MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 222)
#define MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 223)
#define MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 224)
#define MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 225)
#define MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 226)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE0m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 227)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE1m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 228)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE2m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 229)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE3m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 230)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE0m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 231)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE1m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 232)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE2m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 233)
#define MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE3m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 234)
#define MMU_THDU_BST_PORT_XPE0_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 235)
#define MMU_THDU_BST_PORT_XPE0_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 236)
#define MMU_THDU_BST_PORT_XPE1_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 237)
#define MMU_THDU_BST_PORT_XPE1_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 238)
#define MMU_THDU_BST_PORT_XPE2_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 239)
#define MMU_THDU_BST_PORT_XPE2_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 240)
#define MMU_THDU_BST_PORT_XPE3_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 241)
#define MMU_THDU_BST_PORT_XPE3_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 242)
#define MMU_THDU_BST_QGROUP_XPE0_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 243)
#define MMU_THDU_BST_QGROUP_XPE0_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 244)
#define MMU_THDU_BST_QGROUP_XPE1_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 245)
#define MMU_THDU_BST_QGROUP_XPE1_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 246)
#define MMU_THDU_BST_QGROUP_XPE2_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 247)
#define MMU_THDU_BST_QGROUP_XPE2_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 248)
#define MMU_THDU_BST_QGROUP_XPE3_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 249)
#define MMU_THDU_BST_QGROUP_XPE3_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 250)
#define MMU_THDU_BST_QUEUE_XPE0_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 251)
#define MMU_THDU_BST_QUEUE_XPE0_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 252)
#define MMU_THDU_BST_QUEUE_XPE1_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 253)
#define MMU_THDU_BST_QUEUE_XPE1_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 254)
#define MMU_THDU_BST_QUEUE_XPE2_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 255)
#define MMU_THDU_BST_QUEUE_XPE2_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 256)
#define MMU_THDU_BST_QUEUE_XPE3_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 257)
#define MMU_THDU_BST_QUEUE_XPE3_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 258)
#define MMU_THDU_CONFIG_PORT_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 259)
#define MMU_THDU_CONFIG_PORT_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 260)
#define MMU_THDU_CONFIG_PORT_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 261)
#define MMU_THDU_CONFIG_PORT_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 262)
#define MMU_THDU_CONFIG_PORT0_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 263)
#define MMU_THDU_CONFIG_PORT0_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 264)
#define MMU_THDU_CONFIG_PORT0_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 265)
#define MMU_THDU_CONFIG_PORT0_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 266)
#define MMU_THDU_CONFIG_PORT1_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 267)
#define MMU_THDU_CONFIG_PORT1_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 268)
#define MMU_THDU_CONFIG_PORT1_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 269)
#define MMU_THDU_CONFIG_PORT1_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 270)
#define MMU_THDU_CONFIG_QGROUP_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 271)
#define MMU_THDU_CONFIG_QGROUP_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 272)
#define MMU_THDU_CONFIG_QGROUP_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 273)
#define MMU_THDU_CONFIG_QGROUP_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 274)
#define MMU_THDU_CONFIG_QGROUP0_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 275)
#define MMU_THDU_CONFIG_QGROUP0_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 276)
#define MMU_THDU_CONFIG_QGROUP0_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 277)
#define MMU_THDU_CONFIG_QGROUP0_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 278)
#define MMU_THDU_CONFIG_QGROUP1_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 279)
#define MMU_THDU_CONFIG_QGROUP1_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 280)
#define MMU_THDU_CONFIG_QGROUP1_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 281)
#define MMU_THDU_CONFIG_QGROUP1_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 282)
#define MMU_THDU_CONFIG_QUEUE_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 283)
#define MMU_THDU_CONFIG_QUEUE_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 284)
#define MMU_THDU_CONFIG_QUEUE_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 285)
#define MMU_THDU_CONFIG_QUEUE_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 286)
#define MMU_THDU_CONFIG_QUEUE0_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 287)
#define MMU_THDU_CONFIG_QUEUE0_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 288)
#define MMU_THDU_CONFIG_QUEUE0_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 289)
#define MMU_THDU_CONFIG_QUEUE0_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 290)
#define MMU_THDU_CONFIG_QUEUE1_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 291)
#define MMU_THDU_CONFIG_QUEUE1_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 292)
#define MMU_THDU_CONFIG_QUEUE1_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 293)
#define MMU_THDU_CONFIG_QUEUE1_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 294)
#define MMU_THDU_COUNTER_PORT_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 295)
#define MMU_THDU_COUNTER_PORT_XPE0_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 296)
#define MMU_THDU_COUNTER_PORT_XPE1_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 297)
#define MMU_THDU_COUNTER_PORT_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 298)
#define MMU_THDU_COUNTER_PORT_XPE2_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 299)
#define MMU_THDU_COUNTER_PORT_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 300)
#define MMU_THDU_COUNTER_PORT_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 301)
#define MMU_THDU_COUNTER_PORT_XPE3_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 302)
#define MMU_THDU_COUNTER_QGROUP_XPE0_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 303)
#define MMU_THDU_COUNTER_QGROUP_XPE0_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 304)
#define MMU_THDU_COUNTER_QGROUP_XPE1_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 305)
#define MMU_THDU_COUNTER_QGROUP_XPE1_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 306)
#define MMU_THDU_COUNTER_QGROUP_XPE2_PIPE0m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 307)
#define MMU_THDU_COUNTER_QGROUP_XPE2_PIPE1m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 308)
#define MMU_THDU_COUNTER_QGROUP_XPE3_PIPE2m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 309)
#define MMU_THDU_COUNTER_QGROUP_XPE3_PIPE3m                     (BCM56960_A0_MMU_EXTRA_MEM_BASE + 310)
#define MMU_THDU_COUNTER_QUEUE_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 311)
#define MMU_THDU_COUNTER_QUEUE_XPE0_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 312)
#define MMU_THDU_COUNTER_QUEUE_XPE1_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 313)
#define MMU_THDU_COUNTER_QUEUE_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 314)
#define MMU_THDU_COUNTER_QUEUE_XPE2_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 315)
#define MMU_THDU_COUNTER_QUEUE_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 316)
#define MMU_THDU_COUNTER_QUEUE_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 317)
#define MMU_THDU_COUNTER_QUEUE_XPE3_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 318)
#define MMU_THDU_OFFSET_QGROUP_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 319)
#define MMU_THDU_OFFSET_QGROUP_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 320)
#define MMU_THDU_OFFSET_QGROUP_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 321)
#define MMU_THDU_OFFSET_QGROUP_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 322)
#define MMU_THDU_OFFSET_QGROUP0_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 323)
#define MMU_THDU_OFFSET_QGROUP0_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 324)
#define MMU_THDU_OFFSET_QGROUP0_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 325)
#define MMU_THDU_OFFSET_QGROUP0_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 326)
#define MMU_THDU_OFFSET_QGROUP1_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 327)
#define MMU_THDU_OFFSET_QGROUP1_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 328)
#define MMU_THDU_OFFSET_QGROUP1_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 329)
#define MMU_THDU_OFFSET_QGROUP1_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 330)
#define MMU_THDU_OFFSET_QUEUE_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 331)
#define MMU_THDU_OFFSET_QUEUE_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 332)
#define MMU_THDU_OFFSET_QUEUE_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 333)
#define MMU_THDU_OFFSET_QUEUE_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 334)
#define MMU_THDU_OFFSET_QUEUE0_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 335)
#define MMU_THDU_OFFSET_QUEUE0_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 336)
#define MMU_THDU_OFFSET_QUEUE0_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 337)
#define MMU_THDU_OFFSET_QUEUE0_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 338)
#define MMU_THDU_OFFSET_QUEUE1_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 339)
#define MMU_THDU_OFFSET_QUEUE1_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 340)
#define MMU_THDU_OFFSET_QUEUE1_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 341)
#define MMU_THDU_OFFSET_QUEUE1_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 342)
#define MMU_THDU_Q_TO_QGRP_MAP_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 343)
#define MMU_THDU_Q_TO_QGRP_MAP_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 344)
#define MMU_THDU_Q_TO_QGRP_MAP_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 345)
#define MMU_THDU_Q_TO_QGRP_MAP_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 346)
#define MMU_THDU_Q_TO_QGRP_MAP0_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 347)
#define MMU_THDU_Q_TO_QGRP_MAP0_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 348)
#define MMU_THDU_Q_TO_QGRP_MAP0_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 349)
#define MMU_THDU_Q_TO_QGRP_MAP0_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 350)
#define MMU_THDU_Q_TO_QGRP_MAP1_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 351)
#define MMU_THDU_Q_TO_QGRP_MAP1_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 352)
#define MMU_THDU_Q_TO_QGRP_MAP1_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 353)
#define MMU_THDU_Q_TO_QGRP_MAP1_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 354)
#define MMU_THDU_Q_TO_QGRP_MAP2_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 355)
#define MMU_THDU_Q_TO_QGRP_MAP2_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 356)
#define MMU_THDU_Q_TO_QGRP_MAP2_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 357)
#define MMU_THDU_Q_TO_QGRP_MAP2_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 358)
#define MMU_THDU_RESUME_PORT_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 359)
#define MMU_THDU_RESUME_PORT_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 360)
#define MMU_THDU_RESUME_PORT_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 361)
#define MMU_THDU_RESUME_PORT_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 362)
#define MMU_THDU_RESUME_PORT0_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 363)
#define MMU_THDU_RESUME_PORT0_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 364)
#define MMU_THDU_RESUME_PORT0_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 365)
#define MMU_THDU_RESUME_PORT0_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 366)
#define MMU_THDU_RESUME_PORT1_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 367)
#define MMU_THDU_RESUME_PORT1_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 368)
#define MMU_THDU_RESUME_PORT1_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 369)
#define MMU_THDU_RESUME_PORT1_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 370)
#define MMU_THDU_RESUME_PORT2_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 371)
#define MMU_THDU_RESUME_PORT2_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 372)
#define MMU_THDU_RESUME_PORT2_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 373)
#define MMU_THDU_RESUME_PORT2_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 374)
#define MMU_THDU_RESUME_QGROUP_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 375)
#define MMU_THDU_RESUME_QGROUP_XPE0_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 376)
#define MMU_THDU_RESUME_QGROUP_XPE1_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 377)
#define MMU_THDU_RESUME_QGROUP_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 378)
#define MMU_THDU_RESUME_QGROUP_XPE2_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 379)
#define MMU_THDU_RESUME_QGROUP_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 380)
#define MMU_THDU_RESUME_QGROUP_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 381)
#define MMU_THDU_RESUME_QGROUP_XPE3_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 382)
#define MMU_THDU_RESUME_QUEUE_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 383)
#define MMU_THDU_RESUME_QUEUE_XPE0_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 384)
#define MMU_THDU_RESUME_QUEUE_XPE1_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 385)
#define MMU_THDU_RESUME_QUEUE_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 386)
#define MMU_THDU_RESUME_QUEUE_XPE2_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 387)
#define MMU_THDU_RESUME_QUEUE_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 388)
#define MMU_THDU_RESUME_QUEUE_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 389)
#define MMU_THDU_RESUME_QUEUE_XPE3_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 390)
#define MMU_WRED_AVG_QSIZE_XPE0_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 391)
#define MMU_WRED_AVG_QSIZE_XPE0_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 392)
#define MMU_WRED_AVG_QSIZE_XPE1_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 393)
#define MMU_WRED_AVG_QSIZE_XPE1_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 394)
#define MMU_WRED_AVG_QSIZE_XPE2_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 395)
#define MMU_WRED_AVG_QSIZE_XPE2_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 396)
#define MMU_WRED_AVG_QSIZE_XPE3_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 397)
#define MMU_WRED_AVG_QSIZE_XPE3_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 398)
#define MMU_WRED_CONFIG_XPE0_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 399)
#define MMU_WRED_CONFIG_XPE0_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 400)
#define MMU_WRED_CONFIG_XPE1_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 401)
#define MMU_WRED_CONFIG_XPE1_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 402)
#define MMU_WRED_CONFIG_XPE2_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 403)
#define MMU_WRED_CONFIG_XPE2_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 404)
#define MMU_WRED_CONFIG_XPE3_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 405)
#define MMU_WRED_CONFIG_XPE3_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 406)
#define MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE0m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 407)
#define MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE1m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 408)
#define MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE2m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 409)
#define MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE3m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 410)
#define MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE0m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 411)
#define MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE1m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 412)
#define MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE2m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 413)
#define MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE3m                   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 414)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE0m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 415)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE1m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 416)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE2m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 417)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE3m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 418)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE0m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 419)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE1m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 420)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE2m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 421)
#define MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE3m              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 422)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 423)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 424)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 425)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 426)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 427)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 428)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 429)
#define MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 430)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE0m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 431)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE1m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 432)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE2m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 433)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE3m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 434)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE0m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 435)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE1m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 436)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE2m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 437)
#define MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE3m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 438)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE0m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 439)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE1m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 440)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE2m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 441)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE3m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 442)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE0m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 443)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE1m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 444)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE2m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 445)
#define MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE3m                (BCM56960_A0_MMU_EXTRA_MEM_BASE + 446)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE0m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 447)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE1m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 448)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE2m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 449)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE3m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 450)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE0m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 451)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE1m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 452)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE2m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 453)
#define MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE3m             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 454)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE0m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 455)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE1m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 456)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE2m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 457)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE3m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 458)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE0m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 459)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE1m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 460)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE2m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 461)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE3m               (BCM56960_A0_MMU_EXTRA_MEM_BASE + 462)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE0m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 463)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE1m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 464)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE2m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 465)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE3m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 466)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE0m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 467)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE1m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 468)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE2m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 469)
#define MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE3m   (BCM56960_A0_MMU_EXTRA_MEM_BASE + 470)
#define THDI_PORT_PG_BST_XPE0_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 471)
#define THDI_PORT_PG_BST_XPE0_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 472)
#define THDI_PORT_PG_BST_XPE1_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 473)
#define THDI_PORT_PG_BST_XPE1_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 474)
#define THDI_PORT_PG_BST_XPE2_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 475)
#define THDI_PORT_PG_BST_XPE2_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 476)
#define THDI_PORT_PG_BST_XPE3_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 477)
#define THDI_PORT_PG_BST_XPE3_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 478)
#define THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 479)
#define THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 480)
#define THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 481)
#define THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 482)
#define THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 483)
#define THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 484)
#define THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 485)
#define THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 486)
#define THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 487)
#define THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 488)
#define THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 489)
#define THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 490)
#define THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 491)
#define THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 492)
#define THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 493)
#define THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 494)
#define THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 495)
#define THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 496)
#define THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 497)
#define THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 498)
#define THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 499)
#define THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 500)
#define THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 501)
#define THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 502)
#define THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 503)
#define THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 504)
#define THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE0m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 505)
#define THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE3m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 506)
#define THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 507)
#define THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 508)
#define THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE1m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 509)
#define THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE2m                      (BCM56960_A0_MMU_EXTRA_MEM_BASE + 510)
#define THDI_PORT_PG_CONFIG_PIPE0m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 511)
#define THDI_PORT_PG_CONFIG_PIPE1m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 512)
#define THDI_PORT_PG_CONFIG_PIPE2m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 513)
#define THDI_PORT_PG_CONFIG_PIPE3m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 514)
#define THDI_PORT_SP_BST_XPE0_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 515)
#define THDI_PORT_SP_BST_XPE0_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 516)
#define THDI_PORT_SP_BST_XPE1_PIPE0m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 517)
#define THDI_PORT_SP_BST_XPE1_PIPE3m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 518)
#define THDI_PORT_SP_BST_XPE2_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 519)
#define THDI_PORT_SP_BST_XPE2_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 520)
#define THDI_PORT_SP_BST_XPE3_PIPE1m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 521)
#define THDI_PORT_SP_BST_XPE3_PIPE2m                            (BCM56960_A0_MMU_EXTRA_MEM_BASE + 522)
#define THDI_PORT_SP_CNTRS_RT_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 523)
#define THDI_PORT_SP_CNTRS_RT_XPE0_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 524)
#define THDI_PORT_SP_CNTRS_RT_XPE1_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 525)
#define THDI_PORT_SP_CNTRS_RT_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 526)
#define THDI_PORT_SP_CNTRS_RT_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 527)
#define THDI_PORT_SP_CNTRS_RT_XPE2_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 528)
#define THDI_PORT_SP_CNTRS_RT_XPE3_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 529)
#define THDI_PORT_SP_CNTRS_RT_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 530)
#define THDI_PORT_SP_CNTRS_SH_XPE0_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 531)
#define THDI_PORT_SP_CNTRS_SH_XPE0_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 532)
#define THDI_PORT_SP_CNTRS_SH_XPE1_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 533)
#define THDI_PORT_SP_CNTRS_SH_XPE1_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 534)
#define THDI_PORT_SP_CNTRS_SH_XPE2_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 535)
#define THDI_PORT_SP_CNTRS_SH_XPE2_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 536)
#define THDI_PORT_SP_CNTRS_SH_XPE3_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 537)
#define THDI_PORT_SP_CNTRS_SH_XPE3_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 538)
#define THDI_PORT_SP_CONFIG_PIPE0m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 539)
#define THDI_PORT_SP_CONFIG_PIPE1m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 540)
#define THDI_PORT_SP_CONFIG_PIPE2m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 541)
#define THDI_PORT_SP_CONFIG_PIPE3m                              (BCM56960_A0_MMU_EXTRA_MEM_BASE + 542)
#define THDI_PORT_SP_CONFIG0_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 543)
#define THDI_PORT_SP_CONFIG0_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 544)
#define THDI_PORT_SP_CONFIG0_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 545)
#define THDI_PORT_SP_CONFIG0_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 546)
#define THDI_PORT_SP_CONFIG1_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 547)
#define THDI_PORT_SP_CONFIG1_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 548)
#define THDI_PORT_SP_CONFIG1_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 549)
#define THDI_PORT_SP_CONFIG1_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 550)
#define THDI_PORT_SP_CONFIG2_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 551)
#define THDI_PORT_SP_CONFIG2_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 552)
#define THDI_PORT_SP_CONFIG2_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 553)
#define THDI_PORT_SP_CONFIG2_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 554)

#define MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE0m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 555)
#define MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE1m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 556)
#define MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE2m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 557)
#define MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE3m                  (BCM56960_A0_MMU_EXTRA_MEM_BASE + 558)
#define MMU_MTRO_BUCKET_L0_MEM_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 559)
#define MMU_MTRO_BUCKET_L0_MEM_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 560)
#define MMU_MTRO_BUCKET_L0_MEM_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 561)
#define MMU_MTRO_BUCKET_L0_MEM_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 562)
#define MMU_MTRO_BUCKET_L1_MEM_PIPE0m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 563)
#define MMU_MTRO_BUCKET_L1_MEM_PIPE1m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 564)
#define MMU_MTRO_BUCKET_L1_MEM_PIPE2m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 565)
#define MMU_MTRO_BUCKET_L1_MEM_PIPE3m                          (BCM56960_A0_MMU_EXTRA_MEM_BASE + 566)
#define Q_SCHED_L0_ACCUM_COMP_MEM_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 567)
#define Q_SCHED_L0_ACCUM_COMP_MEM_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 568)
#define Q_SCHED_L0_ACCUM_COMP_MEM_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 569)
#define Q_SCHED_L0_ACCUM_COMP_MEM_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 570)
#define Q_SCHED_L0_CREDIT_MEM_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 571)
#define Q_SCHED_L0_CREDIT_MEM_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 572)
#define Q_SCHED_L0_CREDIT_MEM_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 573)
#define Q_SCHED_L0_CREDIT_MEM_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 574)
#define Q_SCHED_L0_WEIGHT_MEM_PIPE0m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 575)
#define Q_SCHED_L0_WEIGHT_MEM_PIPE1m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 576)
#define Q_SCHED_L0_WEIGHT_MEM_PIPE2m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 577)
#define Q_SCHED_L0_WEIGHT_MEM_PIPE3m                           (BCM56960_A0_MMU_EXTRA_MEM_BASE + 578)
#define Q_SCHED_L1_ACCUM_COMP_MEM_PIPE0m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 579)
#define Q_SCHED_L1_ACCUM_COMP_MEM_PIPE1m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 580)
#define Q_SCHED_L1_ACCUM_COMP_MEM_PIPE2m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 581)
#define Q_SCHED_L1_ACCUM_COMP_MEM_PIPE3m                       (BCM56960_A0_MMU_EXTRA_MEM_BASE + 582)
#define Q_SCHED_L1_CREDIT_MEM_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 583)
#define Q_SCHED_L1_CREDIT_MEM_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 584)
#define Q_SCHED_L1_CREDIT_MEM_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 585)
#define Q_SCHED_L1_CREDIT_MEM_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 586)
#define Q_SCHED_L2_ACCUM_COMP_MEM_PIPE0m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 587)
#define Q_SCHED_L2_ACCUM_COMP_MEM_PIPE1m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 588)
#define Q_SCHED_L2_ACCUM_COMP_MEM_PIPE2m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 589)
#define Q_SCHED_L2_ACCUM_COMP_MEM_PIPE3m                         (BCM56960_A0_MMU_EXTRA_MEM_BASE + 590)
#define Q_SCHED_L2_CREDIT_MEM_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 591)
#define Q_SCHED_L2_CREDIT_MEM_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 592)
#define Q_SCHED_L2_CREDIT_MEM_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 593)
#define Q_SCHED_L2_CREDIT_MEM_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 594)
#define MMU_CTR_ING_DROP_MEM_XPE0_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 595)
#define MMU_CTR_ING_DROP_MEM_XPE0_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 596)
#define MMU_CTR_ING_DROP_MEM_XPE1_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 597)
#define MMU_CTR_ING_DROP_MEM_XPE1_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 598)
#define MMU_CTR_ING_DROP_MEM_XPE2_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 599)
#define MMU_CTR_ING_DROP_MEM_XPE2_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 600)
#define MMU_CTR_ING_DROP_MEM_XPE3_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 601)
#define MMU_CTR_ING_DROP_MEM_XPE3_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 602)
#define MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 603)
#define MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 604)
#define MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE0m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 605)
#define MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE3m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 606)
#define MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 607)
#define MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 608)
#define MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE1m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 609)
#define MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE2m                             (BCM56960_A0_MMU_EXTRA_MEM_BASE + 610)

#endif /* BCM56960_A0_BCMTM_SID_ALIAS_H */
